1. Field of the Invention
The invention relates to telecommunication, and in particular, to cyclic redundancy code (CRC) error correction for data received in a mobile device.
2. Description of the Related Art
FIG. 1 shows a conventional mobile device. The architecture shown is simplified to present a data reception path. An antenna 102 receives RF signals, and through an inner receiver 110, the received signal is demodulated to generate an equalizer output. As an example, the inner receiver 110 comprises receiver components such as demodulator 104 and equalizer 106. A channel decoder 112 decodes the equalizer output by FEC (forward error correction) algorithms such as Reed Solomon (RS) code decoding and convolutional code decoding algorithms, and a digital data sequence is output therefrom for post processes. Conventionally, an error checker 114 further checks the data sequence to ensure data integrity. If a CRC error is detected in the data sequence, and the erroneous portion is reparable, the error checker 114 may perform a CRC correction on the data sequence, outputting a corrected data sequence.
FIG. 2 is a flowchart of a conventional data reception method. A data path processed by the mobile device in FIG. 1 is specifically described as follows. In step 202, an equalizer output is generated by the inner receiver 110. In step 204, the equalizer output is de-interlaced and decoded in the channel decoder 112. In step 206, CRC check is performed on the data sequence. If no error is detected, the data sequence is output in step 212. If a CRC error is detected, step 208 is processed to determine whether the CRC error is correctable. If correctable, in step 207, the error checker 114 performs a CRC correction on the data sequence and outputs it in step 212. Otherwise, if not correctable, step 210 discards the data sequence, and reports the error for further exception control.
CRC correction provided by the error checker 114, however, is less than robust. For example, a false data sequence may accidentally generate a correct CRC check result. If the signal quality is poor, the inner receiver 110 generate equalizer outputs with high error rate. Consequently in step 206, the error checker 114 may falsely detect the erroneous data sequence as a correct one based on the nature of CRC algorithm, causing an erroneous data sequence to be output in step 212. Furthermore, a CRC correction process may also render erroneous outputs. For example, CRC correction performed in step 207 may generate a false result from an erroneous input. The false data sequence may cause system failure that degrades system performance. Thus, an enhanced architecture is desirable.